Method for the formation of contact holes for a number of contact regions for components integrated in a substrate

ABSTRACT

A method is disclosed by means of which contact holes (K 1 ), (K 2 ) and (K 3 ), leading to integrated components can be produced with just one structuring mask, contact regions ( 25   e   , 45   e ) in the substrate ( 5 ) and contact holes (K 2 ) lead to contact regions ( 35   c   , 50   c ) located on layer stacks ( 35, 50 ). An auxiliary layer is used for the etching of contact holes (K 1 ), (K 2 ), (K 3 ), which covers a part of the contact holes and thus serves as a selection mask. The auxiliary layer can be structured with a low-resolution lithography in comparison with the mask, such that only one single high-resolution lithography is necessary for the formation of all contact holes (K 1 ), (K 2 ), (K 3 ). The method is particularly suitable for the simultaneous production of contact holes for transistors in the cell field and the logic field of a DRAM.

[0001] The invention lies in the field of integrated circuits andrelates to a method for forming contact holes to a multiplicity ofcontact regions of components integrated in a substrate.

[0002] In the fabrication of integrated circuits, electrical connectionsto the components integrated into a semiconductor substrate arerequired, which connections are generally formed by contact holes filledwith a conductive material. In this case, firstly a planar insulationlayer is applied to the whole area of the semiconductor substrate andthe contact holes are subsequently etched into the insulation layer.

[0003] The integrated components are e.g. MOS transistors having a layerstack—arranged on the semiconductor substrate—comprising a gateelectrode and a gate dielectric which insulates the gate electrode fromthe semiconductor substrate. The source/drain regions of the MOStransistor are situated laterally beside the layer stack in thesemiconductor substrate. Contact is made with the MOS transistors at thegate electrode and also at the source/drain regions. In order toinsulate the gate electrode, the layer stack is completely covered by aninsulating layer, which may be composed e.g. of silicon nitride. Inorder to establish an electrical contact, this insulating layer must beremoved at least from the top side of the gate electrode.

[0004] Constant advances in the miniaturization of the integratedcomponents mean that stringent requirements are imposed on the precisepositioning of the contact holes. In order to meet these requirements, alithography with the highest possible resolution must be used. By meansof the lithography mask structures of a projection mask are projectedonto a radiation-sensitive layer on the semiconductor substrate and saidlayer is subsequently developed in order to remove the irradiatedregions of the radiation-sensitive layer. A mask is produced from theradiation-sensitive layer as a result. Problems in the lithography areposed by the positioning of the projection mask that is to be introducedfor imaging with respect to structures already present on thesemiconductor substrate, since e.g. the contact holes are intended to bepositioned with respect to their contact regions. Errors on account ofmisalignment of the projection mask can be partially compensated for,however, during the subsequent etching of the contact holes. Thedifferent etching properties of the materials of the individualstructures already situated on the semiconductor substrate are utilizedin this case. Such a possibility will be described in more detail belowwith reference to the formation of contact holes to the source/drainregions.

[0005] When forming contact holes to the source/drain regions of a MOStransistor, it can happen that the openings formed in the etching maskare not arranged exactly above the source/drain regions, but ratherslightly displaced laterally with respect to said regions. In this case,the contact holes subsequently to be etched would likewise be laterallydisplaced with respect to the source/drain regions and uncover adjacentstructures, which is undesirable under certain circumstances. In thiscase, it may be problematic e.g. if the insulating layer is removed andthe gate electrode is thereby uncovered. However, provided that theetching method used for forming the contact holes is effected in such away that the material of the insulation layer to be etched is etchedselectively with respect to the material of the mask and the insulatinglayer of the layer stack, then the insulating layer remains on the layerstack and thus protects the gate electrode during etching; the gateelectrode is not uncovered. The contact holes formed in the processdirectly adjoin the insulating layer of the layer stacks, which is whythis type of contact is also referred to as “borderless”. Suchborderless contacts are used quite deliberately in cell arrays ofsemiconductor memories since there the individual layer stacks of theMOS transistors are closely adjacent and have the minimum spacing thatcan be achieved lithographically.

[0006] As already indicated, however, it is also necessary to makecontact with the gate electrode. To that end, it is necessary tointroduce a contact hole into the insulation layer covering the layerstack and to remove the insulating layer covering the gate electrode. Ithas not been possible hitherto to simultaneously fabricate both contactholes, since the insulating layer has to be removed in the contact holeto the gate electrode, but is intended to be preserved in the contacthole to the source/drain regions. Therefore, it has been customary touse two masks which, during the formation of one kind of contact hole,cover the respective other one. In order to meet the required accuraciesin the formation of the contact holes, these two masks must befabricated by means of the same high-resolution lithography. However,the second lithography step that is required means that the probabilityof errors also increases. Furthermore, each high-resolution lithographystep contributes to increasing the expense of the integrated circuit.

[0007] In order to alleviate this problem, in the method which ismentioned in the introduction and described in U.S. Pat. No. 5,792,703,firstly an insulation layer is applied to the semiconductor substrateprovided with the integrated components and borderless contacts to thesource/drain regions in a cell array of a semiconductor memory areproduced in said insulation layer by means of a lithography with a lowerresolution. On account of the configuration of the etching methoddescribed further above, the contacts produced by the lithography with alower resolution are self-aligned with respect to the layer stacks, sothat, despite the relatively large cross sections of the contact holes(the lithography with a lower resolution leads to larger structures),the contact to the source/drain regions is established. After thecontact holes produced in this way have been filled with polysilicon, asecond insulation layer is applied to the filled contact holes and theinsulation layer and contact holes to the contacts which have alreadybeen filled with polysilicon and also to the gate electrodes of thelayer stacks are subsequently produced using a high-resolutionlithography, in order to comply with the required accuracy for thecontacts to the gate electrodes in this case. Consequently, the methodof U.S. Pat. No. 5,792,703 manages with only one high-resolutionlithography. However, relatively stringent requirements with regard tothe alignment of the mask must also be imposed on the lithography with alower resolution used in that case, since only a small offset of themask can be tolerated on account of the relatively closely adjacentstructures in the cell array of the semi-conductor memory. Moreover, itis disadvantageous that two patterning masks are used, i.e. both masksproduce structures that remain on the semiconductor substrate, whichpossibly have a lateral offset with respect to one another. This canhave an adverse effect in particular when masks of subsequentlithography steps have to be aligned with both structural planes.

[0008] In this context, high-resolution lithography is understood tomean a lithography which enables the smallest structures that can beachieved by the technology. Alignment and imaging errors have asignificantly more pronounced effect in the case of this lithographythan in the case of a lithography with a lower resolution. Therefore,the requirements and the error sensitivity are lower in the case oflithography with a lower resolution, and thus so are the associatedcosts due to the lithography method. Since the lithography methods arebeing developed further, the minimum feature size that can be achievedwill also decrease. At present, e.g. 0.13 μm is “state of the art”, andin future it will become 0.1 μm or less. The minimum structures that canbe achieved are larger in the case of a low-resolution lithographymethod than in the case of high-resolution lithography methods, so thatonly “coarser” structures can be produced with lower-resolutionlithography methods.

[0009] Therefore, it is an object of the present invention to specify amethod for forming contact holes to a multiplicity of contact regions ofcomponents integrated in a substrate in which a second patterning maskcan be dispensed with whilst the feature resolution remains the same.

[0010] This object is achieved according to the invention by means of amethod for forming contact holes to a multiplicity of contact regions ofcomponents integrated in a substrate, having the following steps:

[0011] at least one insulation layer is applied over the whole area ofthe substrate having the integrated components;

[0012] a mask with openings is applied to the insulation layer at thelocations at which contact holes reaching as far as the contact regionsare subsequently intended to be formed;

[0013] the contact holes defined through the openings of the mask areetched using the mask in which case, for fully completing the contactholes, at least two etching steps are carried out and an auxiliary layeris used at least in one of the two etching steps, which auxiliary layeris applied to the mask and covers only a portion of the openings, sothat etching is effected only at the locations defined by the uncoveredopenings.

[0014] Accordingly, one essential advantage of the invention is thatjust a single mask is used which already has all the openings for thecontact holes leading to the contact regions. Accordingly, in contrastto U.S. Pat. No. 5,792,703 only one patterning mask is required.Consequently, in the method according to the invention, all the contactholes to be formed are formed with a single common mask, with the resultthat all the contact holes are thus also aligned with respect to oneanother. A possible misalignment of the two masks required in U.S. Pat.No. 5,792,703 and hence a misalignment of the contact holes that are tobe formed with respect to one another is reliably avoided. In order todefine the order of the formation of the individual contact holes or theindividual etching steps, an auxiliary layer is used in addition to themask, which auxiliary layer covers individual openings and thus freesthe uncovered openings for processing. As a result, the uncoveredopenings of the mask are selected, which, in the respective etchingstep, define the position of the contact holes to be formed. Only onelithography method with a low resolution is required for the patterningof the auxiliary layer.

[0015] Since only a single patterning mask is employed, a mask requiredfor a different structural plane can also be aligned uniformly withrespect to all the contact holes.

[0016] Consequently, all the contact holes are fully completed by meansof the mask, in other words all the contact holes reach as far as theirrespective contact regions and the contact regions are uncovered at thebottom of the contact holes.

[0017] The use of the auxiliary layer opens up a degree of freedom forthe method according to the invention, to the extent of the order inwhich, and the etching chemistry with which, the individual contactholes can be fabricated. Depending on the patterning of the auxiliarylayer, that is to say depending on which openings in the mask it covers,individual openings are chosen, so that the partial or completeformation of contact holes is effected only at the uncovered openings.

[0018] Completion in the sense of the invention is understood to meanthe complete formation of the contact holes as far as the uncovering ofthe respective contact regions. This also encompasses a two-stage ormulti-stage etching of individual contact holes. A two-stage ormulti-stage etching may be necessary e.g. when the contact holes have tobe etched through more than a single layer.

[0019] The method according to the invention is preferably distinguishedby the fact that the etching of a portion of the contact holes iscarried out in two partial etching steps, the two partial etching stepscorresponding to the at least two etching steps or one of the at leasttwo etching steps being subdivided into the two partial etching steps,and

[0020] in the first partial etching step, firstly the insulation layeris etched as far as an insulating layer covering the contact regions and

[0021] in the second partial etching step, the insulating layer isremoved to uncover the contact regions, so that the contact holes formedthere penetrate through the insulation layer and the insulating layerand reach as far as contact regions situated beneath the insulatinglayer.

[0022] In the case of at least a portion of the contact holes, theetching is effected in two partial steps since the contact holes have tobe etched through the insulation layer and an insulating layer coveringthe contact regions. In this case, the insulation layer and theinsulating layer are generally composed of different material, with theresult that the etching methods used for etching the individualmaterials have a mutually different etching chemistry. As a rule, theetching method of the first partial etching step for etching theinsulation layer is performed selectively with respect to the insulatinglayer, so that the etching method of the first partial etching stepstops on the insulating layer.

[0023] A further advantageous embodiment is distinguished by the factthat

[0024] the substrate is a semiconductor substrate;

[0025] the components integrated in the semiconductor substrate in eachcase have a layer stack covered with the insulating layer and thecontact regions are arranged on the layer stacks below the insulatinglayer and also in the semiconductor substrate;

[0026] first contact holes reaching as far as the semiconductorsubstrate are etched into the insulation layer at the locations definedby first openings of the mask in a single etching step, the firstcontact holes being formed in a self-aligned manner with respect to thelayer stacks and such that they directly adjoin the latter, and theinsulation layer being etched selectively with respect to the materialof the mask and with respect to the material of the insulating layer ofthe layer stacks, so that side regions of the layer stacks are uncoveredin the first contact holes in the process; and

[0027] second contact holes reaching as far as contact regions situatedon the layer stacks are etched at the locations defined by secondopenings in the mask by means of the two partial etching steps, in whichcase, at least in the second partial etching step, in order to removethe uncovered insulating layer from the bottom of the second contactholes, the first contact holes are covered with the auxiliary layer orare filled with a material at least to an extent such that the layerstack side regions which are uncovered there are completely covered bythe auxiliary layer or the material.

[0028] In order to protect the insulating layer of the layer stackswhich is uncovered in the first contact holes during the removal of theinsulating layer from the second contact holes, the first contact holesare filled with the auxiliary layer or a material to such an extent thatthe insulating layer which is uncovered there is reliably covered. As aresult, the insulating layer in the first contact holes is reliablyprotected.

[0029] The first and second contact holes can be formed successively orjointly. If the second contact holes are formed after the formation ofthe first contact holes, e.g. the second contact holes can be etchedselectively with respect to the material already filled into the firstcontact holes.

[0030] One refinement of the method according to the invention ischaracterized in that, in addition to the first and second openings, themask has third openings at the locations at which, in the insulationlayer, third contact holes reaching as far as further contactregions—arranged in the semiconductor substrate—of the integratedcomponents are intended to be formed, the third openings being producedtogether with the first and second openings during the commonlithography step in the mask, and the third contact holes being etchedtogether with the second contact holes into the insulation layer.

[0031] Consequently, the method according to the invention also enablesfurther contact holes to be produced without additional masks.

[0032] The method according to the invention is found to be particularlyadvantageous in the formation of contact holes in the case of integratedcomponents which are relatively closely adjacent to one another. In thiscase, the method according to the invention is characterized in that

[0033] one portion of the integrated components is arranged in a firstregion of the semiconductor substrate and another portion of theintegrated components is arranged in a second region of thesemiconductor substrate, the layer stacks of the integrated componentsin the first portion being arranged at a smaller distance from oneanother than the layer stacks of the integrated components in the secondportion;

[0034] the first contact holes are formed in the first region of thesemiconductor substrate directly between two adjacent layer stacks andsuch that they directly adjoin the latter;

[0035] the third contact holes are formed in the second region of thesemiconductor component; and

[0036] the second contact holes are formed in both the first and thesecond region of the semiconductor component.

[0037] Such a case occurs e.g. with semiconductor memory componentswhich generally have at least one cell array and a so-called logicarray. Memory cells comprising a selection transistor and a storagecapacitor are arranged in a regular arrangement in the cell array. Onaccount of this regularity, the individual components can be arrangedrelatively close together. Moreover, regular structures can be betterintroduced for imaging by means of the lithography, so that acomparatively high arrangement density of the integrated componentsprevails in the cell array. In contrast to this, the logic array has aless dense arrangement. Therefore, there is also more space there forforming the contact holes which reach as far as the semiconductorsubstrate and which thus need not necessarily be embodied as borderlesscontacts there. Furthermore, it may be possible that the formation ofborderless contacts is actually not possible on account of the irregulararrangement compared with the cell array. In principle, however, it isalso possible to form contact holes that are likewise spaced apart withrespect to the layer stacks in the cell array at the locations at whicha dense arrangement of the integrated components does not prevail.

[0038] In a further refinement of the method according to the invention,during the etching of the first contact holes, the second openings orthe second and third openings of the mask are covered by the auxiliarylayer with the first openings being left uncovered, with the resultthat, after the removal of the auxiliary layer, the second and, ifappropriate, third contact holes can be formed together in the separateetching step. Accordingly, the auxiliary layer is applied to the maskbefore the formation of the first contact holes and is removed againbefore the formation of the second and, if appropriate, third contactholes. The first contact holes are preferably filled with the auxiliarylayer still present. This advantageous refinement of the methodaccording to the invention can also involve the material filled into thefirst contact holes likewise performing the function of the auxiliarylayer and serving as a type of selection mask.

[0039] One advantage of the invention is that a less demandinglithography compared with the lithography for the mask can be used forfabricating the openings that are to be introduced into the auxiliarylayer. Since the auxiliary layer does not define any structures, butrather is intended merely to selectively cover individual openings ofthe mask, the openings of the auxiliary layer can be relatively large incomparison with the openings of the mask. It is favorable e.g. to makethe openings in the auxiliary layer so large that even in the event of apossible misalignment of the projection mask used for fabricating theauxiliary layer, it is always reliably the case that the auxiliary layerdoes not cover the openings of the mask that are to be freed. Moreover,a possible misalignment error of the projection mask used forfabricating the auxiliary layer does not affect subsequent furtherpatterning steps, since the auxiliary layer does not define anypermanent structures. The projection masks used in subsequent patterningsteps can thus be aligned directly with the structures defined by themain mask.

[0040] It has proved to be particularly advantageous if the maskcomprises a first layer and a second layer covering the first layer, thesecond layer being composed of the same material as the insulating layerof the layer stacks. As a result, the etching method, in particular forforming the first contact holes, can be carried out highly selectivelywith respect to the material of the insulating layer.

[0041] In a further refinement, the formation of the second and thirdcontact holes is carried out selectively with respect to the material ofthe first layer of the mask. In this case, the second layer and theinsulating layer uncovered at the bottom of the second contact holes canbe removed simultaneously.

[0042] In a further refinement of the method according to the invention,it has been found to be advantageous if

[0043] the first, second and third contact holes are formed together ina common etching step, the insulating layer being uncovered at thebottom of the second contact holes;

[0044] the first and third contact holes are subsequently covered withan auxiliary layer with the second contact holes being left uncovered;and

[0045] the insulating layer uncovered at the bottom of the secondcontact holes is removed by means of an etching step which is conductedselectively with respect to the material of the auxiliary layer and withrespect to the material of the mask.

[0046] In this case, all the contact holes are formed together andafterward the auxiliary layer is used to select the contact holes inwhich the insulating layer still has to be removed. Thus, the auxiliarylayer likewise serves as a selection mask here.

[0047] The invention is explained in greater detail below usingexemplary embodiments with reference to the figures in which:

[0048]FIGS. 1A-1F show individual method steps of a first exemplaryembodiment;

[0049]FIGS. 2A-2D show individual method steps of a second exemplaryembodiment;

[0050]FIG. 3 shows a semiconductor component fabricated by means of themethod according to the invention; and

[0051]FIG. 4 shows a semiconductor component provided with ametallization.

[0052]FIG. 1A illustrates a semiconductor component (integrated circuit)with a semiconductor substrate 5—composed e.g. of crystallinesilicon—with a multiplicity of integrated components 10, 12, 15, 17, 20.Planar MOS transistors are involved in the present case. Each of thesetransistors respectively has a layer stack (gate stack) 25, 30, 35, 45and 50, each layer stack respectively having a gate oxide 25 a, 30 a, 35a, 45 a, 50 a and a gate electrode 25 b, 30 b, 35 b, 45 b, 50 b which ispreferably composed of polysilicon and, on the side remote from thesemiconductor substrate 5, has a layer made of tungsten silicide 25 c,30 c, 35 c, 45 c, 50 c for reducing the sheet resistance of the gateelectrode and for improving the electrical contact that is subsequentlyto be formed. On its side walls and on its top side, each layer stack25, 30, 35, 45 and 50 is covered by an insulating layer 25 d, 30 d, 35d, 45 d and 50 d, which is preferably constructed in two parts. In thiscase, the insulating layer comprises e.g. self-aligned edge webs and alayer covering the tungsten silicide layer 25 c, 30 c, 35 c, 45 c, 50 c.The self-aligned edge webs (spacers) are formed by conformal depositionand anisotropic etching back of a layer applied over the whole area.Preferably, the insulating layer is composed of silicon nitride. It goeswithout saying that the insulating layer 25 d, 30 d, 35 d, 45 d, 50 dcan also be embodied in one part. The tungsten silicide layer seated onthe gate electrode simultaneously forms the contact regions 25 c, 30 c,35 c, 45 c, 50 c of the layer stacks.

[0053] Doping regions 25 e, 30 e, 45 e, 50 e extend in thesemi-conductor substrate between the individual transistors, said dopingregions forming the source/drain regions of the transistors and, at thesame time, the contact regions integrated into the semiconductorsubstrate 5.

[0054] As can be seen from FIG. 1A, the layer stacks are arranged closertogether in the left-hand half of the figure than in the right-hand halfof the figure. In the left-hand half of the figure, this is intended torepresent a first region ZF of the semiconductor component, whichrepresents a cell array of a semiconductor memory. In contrast to this,the right-hand half of the figure represents a detail of a second regionLF of the same semiconductor component, in which the layer stacks have alarger spacing from one another. The second region LF is e.g. the logicarray (also called periphery) which is required for addressing the cellarray. Consequently, this semiconductor component, which is illustratedby way of example, is a dynamic semiconductor memory (DRAM).

[0055] In the fabrication of the individual contact holes, firstly aplanarizing insulation layer 55, preferably made of an oxide, is appliedto the semiconductor substrate 5 provided with the transistors 10, 12,15, 17, 20. Afterward, as illustrated in FIG. 1B, a mask M comprising afirst and a second layer M1 and M2 is applied. Preferably, the firstlayer M1 is composed of polysilicon and the second layer M2 is composedof silicon nitride. The mask M is preferably formed as a hard mask, i.e.from a material which has significantly greater thermostability incomparison with a photoresist. The materials preferred above for thelayers M1 and M2 satisfy e.g. this requirement.

[0056] The mask M already has all the openings O1, O2, O3 at thelocations at which the first, second and third contact holes K1, K2 andK3 are intended to be formed. In this case, the first contact holes K1serve, in particular, for making contact with the source/drain regionsin the first region (cell array ZF), the third contact holes serve, inparticular, for making contact with the source/drain regions in thesecond region (logic array LF) and the second contact holes serve, inparticular, for making contact with the layer stacks both in the firstand in the second region ZF, LF of the semiconductor component.

[0057] In order to fabricate the openings O1, O2 and O3 in the mask M,use is made of a relatively high-resolution lithography in order toobtain the required accuracy. This may be e.g. a lithography which workswith ultraviolet light. The lithography necessary for achieving therequired accuracy should be employed in each case, that is to say, alithography enabling the contact holes to be placed with sufficientaccuracy with regard to the structures already present (layer stacks,doping regions). The openings of the mask M themselves are formed byapplying e.g. a photoresist, patterning this photoresist by means of thelithography, developing the photoresist in order to remove the exposedregions of the photoresist which define the openings, and etching thefirst and second layers M1, M2 using the patterned photoresist.

[0058] An auxiliary layer HS preferably composed of a photo-sensitiveresist is subsequently applied to the mask M and patterned in such a waythat the auxiliary layer HS leaves uncovered the first openings O1 forforming the first contact holes K1, but covers the second and thirdopenings O2 and O3. A lithography which is less accurate compared withthe lithography of the mask M is required for forming the opening in theauxiliary layer HS. The requirements imposed on the accuracy of thelithography of the auxiliary layer HS are significantly less critical,since larger openings are intended to be formed here in comparison withthe mask M.

[0059] By means of the double mask comprising mask M and auxiliary layerHS, the first contact holes K1 are subsequently etched into theinsulation layer 55, in which case the etching of the insulation layershould be effected selectively with respect to silicon nitride and thephotosensitive resist of the auxiliary layer HS. This can be achieved,for example, by means of the etching gases C₅F₈ and O2. In this case,the etching is carried out until the doping regions situated in thesemiconductor substrate are uncovered. On account of the etching, whichis carried out selectively with respect to silicon nitride, theinsulating layer 25 d and 30 d is not removed in the first contact holesK1, so that the first contact holes are formed in a self-aligned mannerwith respect to, and directly adjoining, the layer stacks 25 and 30situated there. This is effected in particular when the cross section,as can be seen in FIG. 1B, of the first contact holes is larger than thedistance between two directly adjacent layer stacks.

[0060] In a subsequent step, conductive material 60 is filled into thefirst contact holes K1. This is preferably effected with the auxiliarylayer HS still present. Polysilicon, in particular, is suitable asconductive material 60 since good electrical contacts with the dopingregions can be established therewith. After the filling and, ifappropriate, etching back of the polysilicon, in which case, however,the etching back should only be effected to an extent such that theinsulating layer 25 d and 30 d still remains completely covered in thefirst contact holes, the auxiliary layer HS is removed for example byincineration. FIG. 1c shows the semiconductor component after this step.

[0061] Afterward, as shown in FIG. 1D, the insulation layer 55 is etchedselectively with respect to the material (polysilicon in the presentcase) of the first layer M1. The second and third contact holes K2 andK3 are produced in the process. It is favorable if silicon nitride, thematerial of the second mask layer M2, is also removed at the same timeas the etching of the insulation layer 55. This is because an additionaletching step can thus be dispensed with. At the same time, theinsulating layer 35 d and 50 d is also removed in the third contactholes K3 and the tungsten silicide layer 35 c and 50 c serving ascontact regions is thus uncovered. A suitable etching method for etchingthe insulation layer 55—composed for example of silicon oxide—and alsosilicon nitride selectively with respect to polysilicon can be effectedfor example using the etching gases CHF₃ and CF₄ or C₄F₆ or C₄F₈ andalso C₅F₈. Finally, the first mask layer M1 is removed in accordancewith FIG. 1E.

[0062] Lastly, the contact holes K1, K2 and K3 are filled with a furtherconductive material 65, for example tungsten. However, it is alsopossible for this not to be effected until in the context of theformation of the first metallization plane. This modification isillustrated by way of example in FIG. 4, where it can be seen thattrenches 70 connecting individual contact holes have been introducedinto the insulation layer 55 and then, together with the contact holesK1, K2 and K3, have been filled with tungsten. Before the contact holesare filled with tungsten, a thin titanium nitride or titanium/titaniumnitride deposition with subsequent thermal treatment is preferablycarried out in order to reduce the contact resistance with respect tothe silicon substrate 5. During the thermal treatment, titanium silicideis produced at the bottom of the contact holes and forms a good ohmiccontact with the silicon substrate 5. The titanium/titanium nitridelayer which has not been converted into silicide can be removedselectively.

[0063]FIG. 4 furthermore illustrates the alignment of the trenches 70relative to the contact holes. A lithography which is again intended tohave the highest possible resolution is again required in thefabrication of the trenches 70. The projection mask used in this casecan be aligned directly with respect to the contact holes. Since onlyone patterning mask (here mask M) is used, according to the invention,all the contact holes are aligned with respect to one another. An offsetof the kind that may occur when using a plurality of patterning masks isprecluded according to the invention.

[0064] A further exemplary embodiment of the method according to theinvention is shown in FIGS. 2A to 2D. The starting point in this case isa semiconductor substrate which is provided with integratedsemi-conductor components and corresponds to that of FIG. 1A. Afterward,an insulation layer 55 is likewise applied. However, the mask M which isthen deposited onto the insulation layer comprises only one mask layerM1, which is preferably composed of polysilicon. The mask M likewise hasall the openings necessary for forming the contact holes.

[0065] Using the mask M, the insulation layer 55 is then etchedselectively with respect to the material of the mask M (preferablypolysilicon) and with respect to the material of the insulating layer ofthe layer stacks (preferably silicon nitride), in the course of whichthe first, second and third contact holes K1, K2 and K3 are formedjointly. On account of the selectivity, the etching stops on the dopingregions 25 e and 45 e and on the insulating layer 35 d and 55 d.

[0066] Afterward, in accordance with FIG. 2C, an auxiliary layer HS isapplied to the mask M, which, except for the second contact holes K2,covers all the remaining contact holes. As a result, the second contactholes K2 are selected for further treatment, to be precise for theetching of the insulating layer 35 d and 50 d that is subsequently to becarried out. The auxiliary layer HS is patterned in a manner comparableto that in the first exemplary embodiment with a less criticallithography.

[0067] After the removal of the auxiliary layer HS and the mask M,lastly all the contact holes are filled with a conductive material 65,preferably tungsten, and planarized.

[0068] A comparison of the first and second exemplary embodimentsreveals that, by means of the first exemplary embodiment, the firstcontact holes K1 can be filled with a different material, in contrast tothe second and third contact holes K2 and K3. This is advantageous inparticular if a different contact construction than in the logic arrayis desired in the cell array. In the second exemplary embodiment, thereis such a selection possibility with regard to filling materials for thesecond contact holes K2 in comparison with the first and third contactholes K1 and K3, provided that the second contact holes K2 are filledwith a conductive material before the removal of the auxiliary layer HS.

[0069] As can be gathered from FIG. 3, the third contact holes K3 can,at least in part, also be embodied as borderless contacts. Sinceborderless contacts take up less space, it is possible to reduce thesize of the doping regions and thus the transistors in the logic array.If a possible misalignment of the projection mask used for forming theopenings in the mask M causes the contact holes no longer to runcentrally but rather in a laterally displaced manner toward the dopingregions 45 e and 50 e, this lateral offset of the third contact holes K3is compensated for by their self-aligned formation with regard to thelayer stacks 45 and 50.

[0070] In FIG. 3, the second contact holes K2 are shown in a differentplane than the first and third contact holes K1 and K3, which aresituated in the plane of the drawing.

[0071] List of Reference Symbols

[0072]5 Semiconductor substrate

[0073]10, 12, 15, 17, 20 Integrated components/transistors

[0074]25, 30, 35, 40, 45, 50 Layer stack

[0075]25 a, 30 a, 35 a, 45 a, 50 a Gate oxide

[0076]25 b, 30 b, 35 b, 45 b, 50 b Gate electrode

[0077]25 c, 30 c, 35 c, 45 c, 50 c Tungsten silicide layer/contactregion of the layer stacks

[0078]25 d, 30 d, 35 d, 45 d, 50 d Insulating layer

[0079]25 e, 30 e, 45 e, 50 e Doping regions/contact regions in thesemiconductor substrate

[0080]55 Insulation layer

[0081] ZF First region/cell array

[0082] LF Second region/logic array

[0083] M Mask

[0084] M1 First mask layer

[0085] M2 Second mask layer

[0086] O1, O2, O3 First, second and third openings in the mask M

[0087] K1, K2, K3 First, second and third contact holes

[0088] HS Auxiliary layer

[0089]60 Conductive material

[0090]65 Further conductive material

[0091]70 Trenches

1. A method for forming contact holes (K1, K2, K3) to a multiplicity of contact regions (25 e, 30 e, 45 e, 50 e, 5 25 c, 30 c, 35 c, 45 c, 50 c) of components (10, 12, 15, 17, 20) integrated in a substrate, having the following steps: at least one insulation layer (55) is applied over the whole area of the substrate (5) having the integrated components (10, 12, 15, 17, 20); a mask (M) with openings (01, 02, 03) is applied to the insulation layer (55) at the locations at which contact holes (K1, K2, K3) reaching as far as the contact regions (25 e, 30 e, 45 e, 50 e, 25 c, 15 30 c, 35 c, 45 c, 50 c) are subsequently intended to be formed; the contact holes (K1, K2, K3) defined through the openings (O1, 02, 03) of the mask (M) are etched using the mask (M) in which case, for fully completing the contact holes (K1, K2, K3), at least two etching steps are carried out and an auxiliary layer (HS) is used at least in one of the two etching steps, which auxiliary layer is applied to the mask (M) and covers only a portion of the openings (02, 03), so that etching is effected only at the locations defined by the uncovered openings (O1).
 2. The method as claimed in claim 1, characterized in that the etching of a portion carried out in two partial etching steps etching steps or one being subdivided into the and of the contact holes (K2) is partial etching steps, the two corresponding to the at least two of the at least two etching steps two partial etching steps, in the first partial insulation layer (55) is etched as far as an etching step, firstly the insulating layer (35 d, 50 d) covering the contact regions (35 c, 50 c) and in the second partial etching step, the insulating layer (35 d, 50 d) is removed to uncover the contact regions (35 c, 50 c), so that the contact holes (K2) formed there penetrate through the insulation layer (55) and the insulating layer (35 d, 50 d) and reach as far as contact regions (35 c, 50 c) situated beneath the insulating layer (35 d, 50 d).
 3. The method as claimed in claim 2, characterized in that the substrate is a semiconductor substrate (5); the components (10, 12, 15, 17, 20) integrated in the semiconductor substrate (5) in each case have a layer stack (25, 30, 35, 45, 50) covered with the insulating layer (25 d, 30 d, 35 d, 45 d, 50 d) and the contact regions (25 e, 30 e, 45 e, 50 e, 35 c, 50 c) are arranged on the layer stacks (25, 30, 35, 45, 50) below the insulating layer (25 d, 30 d, 35 d, 45 d, 50 d) and also in the semiconductor substrate (5); first contact holes (K1) reaching as far as the semiconductor substrate (5) are etched into the insulation layer at the locations defined by first openings (O1) of the mask (M) in a single etching step, the first contact holes (K1) being formed in a self-aligned manner with respect to the layer stacks (25, 30) and such that they directly adjoin the latter, and the insulation layer (55) being etched selectively with respect to the material of the mask (M) and with respect to the material of the insulating layer (25 d, 30 d) of the layer stacks (25, 30), so that side regions of the layer stacks (25, 30) are uncovered in the first contact holes (K1) in the process; and second contact holes (K2) reaching as far as contact regions (35 c, 50 c) situated on the layer stacks (35, 50) are etched at the locations defined by second openings (O2) in the mask (M) by means of the two partial etching steps, in which case, at least in the second partial etching step, in order to remove the uncovered insulating layer (35 d, 50 d) from the bottom of the second contact holes (K2), the first contact holes are covered with the auxiliary layer (HS) or are filled with a material (60) at least to an extent such that the layer stack side regions which are uncovered there are completely covered by the auxiliary layer (HS) or the material (60).
 4. The method as claimed in claim 3, characterized in that, in addition to the first and second openings (O1, 02), the mask (M) has third openings (03) at the locations at which, in the insulation layer (55), third contact holes (K3) reaching as far as further contact regions (45 e)—arranged in the semiconductor substrate (5)—of the integrated components are intended to be formed, the third contact holes (K3) being etched together with the second contact holes (K2) into the insulation layer (55).
 5. The method as claimed in claim 4, characterized in that one portion of the integrated components (10, 12, 15) is arranged in a first region (ZF) of the semiconductor substrate (5) and another portion of the integrated components (17, 20) is arranged in a second region (LF) of the semiconductor substrate (5), the layer stacks (25, 30, 35) of the integrated components (10, 12, 15) in the first portion (ZF) being arranged at a smaller distance from one another than the layer stacks (45, 50) of the integrated components (17, 20) in the second portion (LF); the first contact holes (K1) are formed in the first region (ZF) of the semiconductor substrate directly between two adjacent layer stacks (25, 30, 35) and such that they directly adjoin the latter; the third contact holes (K3) are formed in the second region (LF) of the semiconductor substrate; and the second contact holes (K2) are formed in both the first and the second region (ZF, LF) of the semiconductor substrate.
 6. The method as claimed in claim 3, characterized in that, during the etching of the first contact holes (K1), the second openings (02) of the mask (M) are covered by the auxiliary layer (HS), with the first openings (O1) being left uncovered, and, after the removal of the auxiliary layer (HS) the second contact holes (K2) are formed in the subsequent separate etching step.
 7. The method as claimed in claim 4, characterized in that, during the etching of the first contact holes (K1), the second and third openings (02, 03) of the mask (M) covered by the auxiliary layer (HS) with the first openings (O1) being left uncovered, and, after the removal of the auxiliary layer (HS), the second and third contact holes (K2, K3) are formed together in the separate etching step.
 8. The method as claimed in claim 1, characterized in that the mask (M) comprises a first layer and a second (M2) covering the first layer (M1), the second (M2) being composed of the same material as the preceding layer insulating layer (25 d, 30 d, 35 d, 45 d, 50 d) of the layer stacks (25, 30, 35, 45, 50).
 9. The method as claimed in claim 8, characterized in that the material of the second layer (M2) and the material of the insulating layer (25 d, 30 d, 35 d, 45 d, 50 d) is predominantly silicon nitride.
 10. The method as claimed in claim 8, characterized in that the second and third contact holes (K2, K3) are formed by means of an etching which is conducted selectively with respect to the material of the first layer (M1) of 15 the mask (M) and in which, at the same time, the insulating layer (35 d, 50 d) uncovered at the bottom of the second contact holes (K2) and the second layer (M2) of the mask (M) are removed.
 11. The method as claimed in claim 8, characterized in that the material of the first layer (M1) of the mask (M) is predominantly polysilicon.
 12. The method as claimed in claim 3, characterized in that for the purpose of filling the first contact holes (K1), a conductive material (60) is used which comes into electrical contact with the contact regions (25 e) uncovered at the bottom of the first contact hole (K1).
 13. The method as claimed in claim 12, characterized in that the conductive material (60) is polysilicon.
 14. The method as claimed in claim 12, characterized in that the first contact holes (K1) which are only partially filled with the conductive material (60), and also the second and third contact holes (K2, K3) are completely filled with a further electrically conductive material (65) for making electrical contact with the first, second and third contact regions (25 e, 30 e, 45 e, 50 e, 35 c, 50 c).
 15. The method as claimed in claim 14, characterized in that the further electrically conductive material (65) is predominantly tungsten.
 16. The method as claimed in claim 4, characterized in that the first, second and third contact holes (K1, are formed together in a common etching step, insulating layer (35 d, 50 d) being uncovered at bottom of the second contact holes (K2); the first and third contact holes (K1, K3) are auxiliary layer (HS) (K2) being left the K3) the subsequently covered with an with the second contact holes uncovered; and the insulating layer (35 d, 50 d)K2, uncovered at the bottom of the second contact holes (K2) is removed by means of an etching step which is conducted selectively with respect to the material of the auxiliary layer (HS) and with respect to the material of the mask (M).
 17. The method as claimed in claim 16, characterized in that, after the removal of the insulating layer (35 d, 50 d) from the bottom of the second contact holes (K2), the auxiliary layer (HS)is removed and the first, second and third contact holes (K1, K2, K3)are then filled with an electrically conductive material (65) which comes into electrical contact holes with the contact regions (25 e, 30 e, 45 e, 50 e) uncovered at the bottom of the first, second and third contact holes (K1, K2, K3).
 18. The method as claimed in claim 17, characterized in that the electrically conductive material (65) is predominantly tungsten.
 19. The method as claimed in claim 4, characterized in that the third contact holes (K3) are formed as contact holes which are self-aligned with respect to the layer 15 stacks (45), directly adjoin the latter and reach as far as the semiconductor substrate (5).
 20. The method as claimed in claim 1, characterized in that the layer stacks (10, 12, 15, 17, 20) have, at their side facing toward the semiconductor substrate (5), in each case a gate oxide (25 a, 30 a, 35 a, 45 a, 50 a),above that a gate electrode (25 b, 30 b, 35 b, 45 b, 50 b) composed of polysilicon—with a tungsten silicide layer (25 c, 30 c, 35 c, 45 c, 50 c), the layer stacks (10, 12, 15, 17, 20) being covered by the insulating layer (25 d, 30 d, 35 d, 45 d, 50 d)at their side walls and their side remote from the semiconductor substrate (5).
 21. The method as claimed in claim 1, characterized in that the insulation layer (55) is composed of an oxide.
 22. The method as claimed in claim 1, characterized in that the openings (O1, 02, 03) of the mask (M) are produced in a common first lithography method, and the auxiliary layer (HS) is patterned by a second lithography method, in which case the feature resolution of the first lithography method is higher than that of the second lithography method.
 23. The method as claimed in claim 1, characterized in that the auxiliary layer (HS) is composed of a photoresist. 